To work on next generation with latest process technology of Intel, and work on next generation of mix-process node integration technology to enable various computing accelerator integration, in the era of hyper scale computing. Define VLSI Structural Design methodology and developing design flows. Implement structural physical designs, such as synthesis, floor planning, power-grid and clock tree designs, timing budgeting and closure, place and route, RC-extraction and integration. Verify structural physical designs, such as functional equivalency, timing/performance, noise, layout design rules, reliability and power.
You should possess a relevant educational qualification, BSEE or equivalent with 8+ years/MSEE or equivalent with 6+ years design experience in the structural/physical design domain.
Additional qualifications include:
Have multiple tape-out experience in deep submicron, preferably experience in 14nm and below
Must have in depth, extensive knowledge and hands-on experience in high speed design building block for Synthesis, Place and Route, clock tree synthesis and Static timing analysis.
Cross-discipline knowledge in any of these areas, such as Floor planning, Power-grid, Reliability Verification and handling Analog specification.
Understanding of design challenges in latest technology process nodes.
Some architecture knowledge in DDR PHY or High speed IO PHY design.
Experience in relevant VLSI structural/physical design methodology, flows and relevant EDA tools.
Experienced in industry Synthesis and PnR tools: DC-Compiler, ICCompileII and ICCompiler
Hands-on expertise with scripting languages such as Perl, TCL, and knowledge of hardware description languages of VHDL & Verilog.